Instructions:
- The marks are indicated in the right-hand margin.
- There are NINE questions in this paper.
- Attempt FIVE questions in all.
- Question No. 1 is compulsory.
Questions
Answer the following:
Answer of the following questions (any seven only):
Answer the following:
Answer the following:
Answer the following:
Answer the following:
Answer the following:
Answer the following:
Answer the following:
Answer the following:
Write short notes on the following:
Q.1 Answer of the following questions (any seven only):- [2 x 7 = 14]
(a) What is the use of K-map?
(b) Discuss Universal gates.
(c) Add hexadecimal number 2ABC & 98F2.
(d) Number of 2:1 mux requires designing 256:1 mux is .........
(e) Find 2's complement of 101101.
(f) What is the function of a sample-and-hold circuit?
(g) Define term propagation delay.
(h) Define race around condition in JK flip flop.
(i) What is the purpose of expanding memory size?
(j) Differentiate between ROM and RAM.
Q.2 (a) Realize XNOR logic function using NAND gate only.
(b) Simplify Y = ABC + AB'C + A'BC
Q.3 A logic circuit has four inputs A, B, C, D and output Y. Y=1 when A & B are both subjected to the condition that C and D are both low or both high. Design the logic circuit.
Q.4 (a) Design 8 to 3 line Encoder circuit.
(b) Implement NAND gate using TTL logic family.
Q.5 (a) Design a parallel-to-serial converter using shift registers and explain its operation.
(b) Compare the characteristics and applications of JK and T flip-flops.
Q.6 (a) Explain the working principle of an R-2R ladder DAC with a detailed diagram.
(b) Design a 3-bit flash ADC and explain its working with an example.
Q.7 (a) Find the Simplified logical expression for Y.
Y (A, B, C, D, E) = ∑m (0, 2, 4, 7, 8, 10, 12, 16, 18, 20, 23, 24, 25, 26, 27, 28)
(b) Summarize the design procedure for a synchronous sequential circuit.
Q.8 (a) Implement S-R, T, D flip-flops using J-K flip-flop. Also show the implementation with help of State Tables.
(b) Discuss the organization and operation of content-addressable memory (CAM).
Q.9 Write short notes on the following: [7 x 2 = 14]
(a) Binary Parallel Adder
(b) Digital IC logic families
Instructions:
- The marks are indicated in the right-hand margin.
- There are NINE questions in this paper.
- Attempt FIVE questions in all.
- Question No. 1 is compulsory.
Q.1 Answer of the following questions (any seven only):
What is the use of K-map?
Discuss Universal gates.
Add hexadecimal number 2ABC & 98F2.
Number of 2:1 mux requires designing 256:1 mux is .........
Find 2's complement of 1011011.
What is the function of a sample-and-hold circuit?
Define term propagation delay.
Define race around condition in JK flip flop.
What is the purpose of expanding memory size?
Differentiate between ROM and RAM.
Q.2 Solve both questions :
Realize XNOR logic function using NAND gate only.
Simplify $ Y = ABC + AB\overline{C} + A\overline{B}C $
Q.3 Solve this question :
A logic circuit has four inputs A, B, C, D and output Y. Y = 1 when A & B are both 1 subjected to the condition that C and D are both low or both high. Design the logic circuit.
Q.4 Solve both questions :
Design 8 to 3 line Encoder circuit.
Implement NAND gate using TTL logic family.
Q.5 Solve both questions :
Design a parallel-to-serial converter using shift registers and explain its operation.
Compare the characteristics and applications of JK and T flip-flops.
Q.6 Solve both questions :
Explain the working principle of an R-2R ladder DAC with a detailed diagram.
Design a 3-bit flash ADC and explain its working with an example.
Q.7 Solve both questions :
Find the Simplified logical expression for Y.
$ Y (A, B, C, D, E) = \Sigma m $(0, 2, 4, 7, 8, 10, 12, 16, 18, 20, 23, 24, 25, 26, 27, 28)
Summarize the design procedure for a synchronous sequential circuit.
Q.8 Solve both questions :
Implement S-R, T, D flip-flops using J-K flip-flop. Also show the implementation with help of State Tables.
Discuss the organization and operation of content-addressable memory (CAM).
Q.9 Write short notes on the following:
(a) Binary Parallel Adder
(b) Digital IC logic families
Instructions:
- The marks are indicated in the right-hand margin.
- There are NINE questions in this paper.
- Attempt FIVE questions in all.
- Question No. 1 is compulsory.
Q.1 Answer of the following questions (any seven only):
What is the use of K-map?
Discuss Universal gates.
Add hexadecimal number 2ABC & 98F2.
Number of 2:1 mux requires designing 256:1 mux is .........
Find 2's complement of 1011011.
What is the function of a sample-and-hold circuit?
Define term propagation delay.
Define race around condition in JK flip flop.
What is the purpose of expanding memory size?
Differentiate between ROM and RAM.
Q.2 Solve both questions :
Realize XNOR logic function using NAND gate only.
Simplify $ Y = ABC + AB\overline{C} + A\overline{B}C $
Q.3 Solve this question :
A logic circuit has four inputs A, B, C, D and output Y. Y = 1 when A & B are both 1 subjected to the condition that C and D are both low or both high. Design the logic circuit.
Q.4 Solve both questions :
Design 8 to 3 line Encoder circuit.
Implement NAND gate using TTL logic family.
Q.5 Solve both questions :
Design a parallel-to-serial converter using shift registers and explain its operation.
Compare the characteristics and applications of JK and T flip-flops.
Q.6 Solve both questions :
Explain the working principle of an R-2R ladder DAC with a detailed diagram.
Design a 3-bit flash ADC and explain its working with an example.
Q.7 Solve both questions :
Find the Simplified logical expression for Y.
$ Y (A, B, C, D, E) = \Sigma m $(0, 2, 4, 7, 8, 10, 12, 16, 18, 20, 23, 24, 25, 26, 27, 28)
Summarize the design procedure for a synchronous sequential circuit.
Q.8 Solve both questions :
Implement S-R, T, D flip-flops using J-K flip-flop. Also show the implementation with help of State Tables.
Discuss the organization and operation of content-addressable memory (CAM).
Q.9 Write short notes on the following:
(a) Binary Parallel Adder
(b) Digital IC logic families
Instructions:
- The marks are indicated in the right-hand margin.
- There are NINE questions in this paper.
- Attempt FIVE questions in all.
- Question No. 1 is compulsory.
Q.1 Answer any seven question only:
Define Dynamic RAM.
The resolution of a 10-bit AD converter for an input range of 10 V is approximately _________
The parameter through which 16 distinct values can be represented is known as _________
Define Multiplexing.
Write the significance of Truth table.
Write the differences between Combinational and Sequential circuit.
A hexadecimal odometer displays F52F. The next reading will be _________
The basic property of Sequential circuit is _________
How many entries will be in the truth table of a 4-input NAND gate?
What is Dual Slope ADC?
Q.2 Solve this question :
What are weighted, non-weighted, cyclic and self-complementary codes? Explain each with examples.
Q.3 Solve this question :
Design a BCD to 7-segment display decoder circuit using logic gates.
Q.4 Solve this question :
Design a 3-bit parallel comparator A/D convertor that provides output in 2's complement format.
Q.5 Solve both questions :
Design full adder using 8:1 mux.
Design full adder using 4:1 mux.
Q.6 Solve this question :
What is binary shift register? Write down their application.
Q.7 Solve this question :
Minimize the following expression using k-map
Q.8 Solve this question :
Describe the procedure to design Mod-6 counter.
Q.9 Write short notes on any two of the following:
Instructions:
- The marks are indicated in the right-hand margin.
- There are NINE questions in this paper.
- Attempt FIVE questions in all.
- Question No. 1 is compulsory.
Q.1 Answer any seven question only:
Define Dynamic RAM.
The resolution of a 10-bit AD converter for an input range of 10 V is approximately _________
The parameter through which 16 distinct values can be represented is known as _________
Define Multiplexing.
Write the significance of Truth table.
Write the differences between Combinational and Sequential circuit.
A hexadecimal odometer displays F52F. The next reading will be _________
The basic property of Sequential circuit is _________
How many entries will be in the truth table of a 4-input NAND gate?
What is Dual Slope ADC?
Q.2 Solve this question :
What are weighted, non-weighted, cyclic and self-complementary codes? Explain each with examples.
Q.3 Solve this question :
Design a BCD to 7-segment display decoder circuit using logic gates.
Q.4 Solve this question :
Design a 3-bit parallel comparator A/D convertor that provides output in 2's complement format.
Q.5 Solve both questions :
Design full adder using 8:1 mux.
Design full adder using 4:1 mux.
Q.6 Solve this question :
What is binary shift register? Write down their application.
Q.7 Solve this question :
Minimize the following expression using k-map
$ f(P,Q,R,S) = \Sigma m(0,1,4,5,7,12,13) $
Q.8 Solve this question :
Describe the procedure to design Mod-6 counter.
Q.9 Write short notes on any two of the following:
Instructions:
- The marks are indicated in the right-hand margin.
- There are NINE questions in this paper.
- Attempt FIVE questions in all.
- Question No. 1 is compulsory.
Q.1 Answer any seven Question only:
Draw Truth table of JK flip flop.
Convert the Decimal number (108.025) to their binary equivalent.
Draw the truth table and logic circuit of Half-adder.
Write the difference between combinational & Sequential circuit.
Draw timing diagram of SR flip-flop.
Find 2's complement of 1011011.
Number of 2:1 mux requires designing 256:1 mux is
Add hexadecimal number 2ABC & 98F2.
Discuss Universal gates.
What is the use of K-map?
Q.2 Solve this question :
Implement the following function using only NAND gate $ F(A,B,C)=\Sigma m(0,1,2,3,7) $.
Q.3 Solve both questions :
Realize XNOR logic function using NAND gate only.
Simplify $ Y=ABC+AB\overline{C}+A\overline{B}C $
Q.4 Solve this question :
A logic circuit has four inputs A,B,C,D and output Y. Y=1 when A & B are both 1, subjected to the condition that C and D are both low or both high. Design the logic circuit.
Q.5 Solve this question :
Explain Master-slave flip flop. What are race around condition?. How it can be circumvented with the help of Master-slave flip flop.
Q.6 Solve both questions :
Design 8 to 3 line Encoder circuit.
Implement NAND gate using TTL logic family.
Q.7 Solve this question :
Summarize the design procedure for a synchronous sequential circuit.
Q.8 Solve both questions :
Explain the working of R-2R Ladder DAC.
Design 3-bit binary counter using T flip-flop.
Q.9 Write short notes on the following:
(a) Binary Parallel Adder
(b) Digital IC logic families
Instructions:
- The marks are indicated in the right-hand margin.
- There are NINE questions in this paper.
- Attempt FIVE questions in all.
- Question No. 1 is compulsory.
Q.1 Answer any seven Question only:
Draw Truth table of JK flip flop.
Convert the Decimal number (108.025) to their binary equivalent.
Draw the truth table and logic circuit of Half-adder.
Write the difference between combinational & Sequential circuit.
Draw timing diagram of SR flip-flop.
Find 2's complement of 1011011.
Number of 2:1 mux requires designing 256:1 mux is
Add hexadecimal number 2ABC & 98F2.
Discuss Universal gates.
What is the use of K-map?
Q.2 Solve this question :
Implement the following function using only NAND gate $ F(A,B,C)=\Sigma m(0,1,2,3,7) $.
Q.3 Solve both questions :
Realize XNOR logic function using NAND gate only.
Simplify $ Y=ABC+AB\overline{C}+A\overline{B}C $
Q.4 Solve this question :
A logic circuit has four inputs A,B,C,D and output Y. Y=1 when A & B are both 1, subjected to the condition that C and D are both low or both high. Design the logic circuit.
Q.5 Solve this question :
Explain Master-slave flip flop. What are race around condition?. How it can be circumvented with the help of Master-slave flip flop.
Q.6 Solve both questions :
Design 8 to 3 line Encoder circuit.
Implement NAND gate using TTL logic family.
Q.7 Solve this question :
Summarize the design procedure for a synchronous sequential circuit.
Q.8 Solve both questions :
Explain the working of R-2R Ladder DAC.
Design 3-bit binary counter using T flip-flop.
Q.9 Write short notes on the following:
(a) Binary Parallel Adder
(b) Digital IC logic families
Instructions:
- The marks are indicated in the right-hand margin.
- There are NINE questions in this paper.
- Attempt FIVE questions in all.
- Question No. 1 is compulsory.
- Assume suitable data if required.
Questions
Answer the following:
Answer any seven of the following as directed:
Answer the following:
Answer the following:
Answer the following:
Answer the following:
Answer the following:
Answer the following:
Answer the following:
Answer the following:
Instructions:
- The marks are indicated in the right-hand margin.
- There are NINE questions in this paper.
- Attempt FIVE questions in all.
- Question No. 1 is compulsory.
Q.1 Choose the correct answer of the following (any seven):
Dynamic RAM employs
The resolution of a 10-bit AD converter for an input range of 10 V is approximately
The evolution of PLD begins with
The parameter through which 16 distinct values can be represented is known as
The number of full and half adders required to add 16-bit number is
If we record any music in any recorder, such type of process is called
The no. of D flip-flop required to form a 5-bit ring counter is
An overflow is a/an
The systematic reduction of logic circuits is accomplished by
A latch is an example of a/an
Q.2 Solve both questions :
(a) Design an excess-3 to BCD code converter using minimum number of NAND gates.
(b) Prove the following:
$ A \oplus B = \overline{A} \oplus \overline{B} $
$ A \oplus \overline{B} = \overline{A \oplus B} = \overline{A} \oplus B $
Q.3 Solve both questions :
(a) How can we implement preset and clear inputs in a flip-flop? Explain with the help of a diagram and list their uses.
(b) Design a Mod 9 counter using T flip-flops.
Q.4 Solve both questions :
(a) Explain internal organization of $ 16 \times 2 $ memory chips using suitable diagrams. Calculate the maximum rate at which data can be stored and read for a memory having following timing parameters:
| Parameter | Time (ns) |
|---|---|
| Read to Output Valid Time $ (t_{RD}) $ | 70 |
| Data Setup Time $ (t_{DW}) $ | 120 |
| Read to Cycle Time $ (t_{RC}) $ | 200 |
| Write Release Time $ (t_{WR}) $ | 0 |
| Write Cycle $ (t_{WC}) $ | 200 |
(b) Differentiate between Word Capacity and Word Size. Design a $ 16 \times 8 $ CAM, using $ 8 \times 2 $ CAM chips.
Q.5 Solve both questions :
(a) Define resolution, linearity, accuracy and settling time of D/A converters. A typical D/A converter has a full-scale analog output of 10 V and accepts 6 binary bits as input. What will be the voltage corresponding to each analog step?
(b) Design a 3-bit parallel comparator A/D converter that provides output in 2's complement format.
Q.6 Solve both questions :
(a) Design a BCD to 7-segment display decoder circuit using logic gates.
(b) Design full adder using the following: (i) 8:1 mux (ii) 4:1 mux
Q.7 Solve both questions :
(a) On the following graph, inputs CLK and D are shown: . They are inputs to a D latch and a positive edge triggered D flip-flop. Assuming initial output 0, draw the output waveform for flip-flop and latch. Do the two outputs differ? If so, why?
(b) Explain SIPO and SISO operations of shift register with relevant logic diagrams and truth tables.
Q.8 Solve both questions :
(a) Identify the following logic functions implemented at F:
(b) Implement the following CMOS logics:
(i) $ \overline{AB(A+B)} $
(ii) $ \overline{((CD) + B)A} $
Q.9 Solve both questions :
(a) What are weighted, non-weighted, cyclic and self-complementary codes? Explain each with examples.
(b) Find the values of X in the following conversions:
(i) $ (95.10)_{10} $ to $ (X)_2 $
(ii) $ (70)_8 $ to $ (X)_2 $
(iii) $ (168.16)_8 $ to $ (X)_{16} $
Instructions:
- The marks are indicated in the right-hand margin.
- There are NINE questions in this paper.
- Attempt FIVE questions in all.
- Question No. 1 is compulsory.
Q.1 Choose the correct answer of the following (any seven):
Dynamic RAM employs
The resolution of a 10-bit AD converter for an input range of 10 V is approximately
The evolution of PLD begins with
The parameter through which 16 distinct values can be represented is known as
The number of full and half adders required to add 16-bit number is
If we record any music in any recorder, such type of process is called
The no. of D flip-flop required to form a 5-bit ring counter is
An overflow is a/an
The systematic reduction of logic circuits is accomplished by
A latch is an example of a/an
Q.2 Solve both questions :
(a) Design an excess-3 to BCD code converter using minimum number of NAND gates.
(b) Prove the following:
$ A \oplus B = \overline{A} \oplus \overline{B} $
$ A \oplus \overline{B} = \overline{A \oplus B} = \overline{A} \oplus B $
Q.3 Solve both questions :
(a) How can we implement preset and clear inputs in a flip-flop? Explain with the help of a diagram and list their uses.
(b) Design a Mod 9 counter using T flip-flops.
Q.4 Solve both questions :
(a) Explain internal organization of $ 16 \times 2 $ memory chips using suitable diagrams. Calculate the maximum rate at which data can be stored and read for a memory having following timing parameters:
| Parameter | Time (ns) |
|---|---|
| Read to Output Valid Time $ (t_{RD}) $ | 70 |
| Data Setup Time $ (t_{DW}) $ | 120 |
| Read to Cycle Time $ (t_{RC}) $ | 200 |
| Write Release Time $ (t_{WR}) $ | 0 |
| Write Cycle $ (t_{WC}) $ | 200 |
(b) Differentiate between Word Capacity and Word Size. Design a $ 16 \times 8 $ CAM, using $ 8 \times 2 $ CAM chips.
Q.5 Solve both questions :
(a) Define resolution, linearity, accuracy and settling time of D/A converters. A typical D/A converter has a full-scale analog output of 10 V and accepts 6 binary bits as input. What will be the voltage corresponding to each analog step?
(b) Design a 3-bit parallel comparator A/D converter that provides output in 2's complement format.
Q.6 Solve both questions :
(a) Design a BCD to 7-segment display decoder circuit using logic gates.
(b) Design full adder using the following: (i) 8:1 mux (ii) 4:1 mux
Q.7 Solve both questions :
(a) On the following graph, inputs CLK and D are shown: . They are inputs to a D latch and a positive edge triggered D flip-flop. Assuming initial output 0, draw the output waveform for flip-flop and latch. Do the two outputs differ? If so, why?
(b) Explain SIPO and SISO operations of shift register with relevant logic diagrams and truth tables.
Q.8 Solve both questions :
(a) Identify the following logic functions implemented at F:
(b) Implement the following CMOS logics:
(i) $ \overline{AB(A+B)} $
(ii) $ \overline{((CD) + B)A} $
Q.9 Solve both questions :
(a) What are weighted, non-weighted, cyclic and self-complementary codes? Explain each with examples.
(b) Find the values of X in the following conversions:
(i) $ (95.10)_{10} $ to $ (X)_2 $
(ii) $ (70)_8 $ to $ (X)_2 $
(iii) $ (168.16)_8 $ to $ (X)_{16} $
Instructions:
- The marks are indicated in the right-hand margin.
- There are NINE questions in this paper.
- Attempt FIVE questions in all.
- Question No. 1 is compulsory.
Questions
Answer the following:
Choose the correct answer from the following (any seven):
Answer the following:
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Write short notes on any two of the following:
Instructions:
- The marks are indicated in the right-hand margin.
- There are NINE questions in this paper.
- Attempt FIVE questions in all.
- Question No. 1 is compulsory.
Questions
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Choose the correct answer from the following (any seven):
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Instructions:
- The marks are indicated in the right-hand margin.
- There are NINE questions in this paper.
- Attempt FIVE questions in all.
- Question No. 1 is compulsory.
Questions
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Choose the correct option of the following (any seven) :
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Instructions:
- There are Nine Questions in this Paper.
- Attempt Five questions in all.
- Question No. 1 is Compulsory.
- The marks are indicated in the right-hand margin.
Questions
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Fill in the blanks.
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Write notes on following-
Instructions:
- There are Nine Questions in this Paper.
- Attempt Five questions in all.
- Question No. 1 is Compulsory.
- The marks are indicated in the right hand margin.
Questions
Answer the following:
Choose the correct option of the following (any seven):
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Write a short notes on any two :
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Instructions:
- The marks are indicated in the right-hand margin.
- There are NINE questions in this paper.
- Attempt FIVE questions in all.
- Question No. 1 is compulsory.
Questions
Answer the following:
Fill in the blanks (any seven) :
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Answer the following:
Write notes on the following :
Instructions:
- The marks are indicated in the right-hand margin.
- There are NINE questions in this paper.
- Attempt FIVE questions in all.
- Question No. 1 is compulsory.
Questions
Answer the following:
Choose the correct option from any seven of the following :
Answer the following:
Answer the following:
Answer the following:
Answer the following:
Answer the following:
Answer the following:
Answer the following:
Answer the following:
Write short notes on any two of the following :
Instructions:
- The marks are indicated in the right-hand margin.
- There are NINE questions in this paper.
- Attempt FIVE questions in all.
- Question No. 1 is compulsory.
Questions
Choose the correct option from the following (any seven) :
Answer the following:
Answer the following:
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Write short notes on any two of the following :
Instructions:
- All questions carry equal marks.
- There are NINE questions in this paper.
- Attempt FIVE questions in all.
- Question No. 1 is compulsory.
Questions
Choose the correct answer (any seven) :
Answer the following:
Answer the following:
Answer the following:
Answer the following:
Design a mod-8 up-down counter.
Answer the following:
A digital system has four bits of a 4-bit word as inputs. The output is equal to 1 when any two adjacent bits are 1, or any three or all four bits are 1.
Write short notes on the following :