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2024 1054012024 V2 105401

2024105401

B.Tech 4th Semester Examination, 2024

03 Hours70 marks

Instructions

  • The marks are indicated in the right-hand margin.
  • There are NINE questions in this paper.
  • Attempt FIVE questions in all.
  • Question No. 1 is compulsory.

Q.1 Choose the correct answer of the following (any seven question only):

Ask AI

  1. Q1.1

    What is the first step in the instruction execution cycle?

    a)

    Decode

    b)

    Execute

    c)

    Fetch

    d)

    Store

    Ask AI

  2. Q1.2

    What is the advantage of carry look-ahead adders over ripple carry adders?

    a)

    Simplicity in design

    b)

    Increased latency

    c)

    Reduced power consumption

    d)

    Faster addition by reducing carry propagation delay

    Ask AI

  3. Q1.3

    Which type of control unit is faster but more difficult to modify?

    a)

    Hardwired Control Unit

    b)

    Microprogrammed Control Unit

    c)

    Cache Control Unit

    d)

    Memory Management Unit

    Ask AI

  4. Q1.4

    Which of the following I/O transfer methods involves the CPU polling the device until data is ready?

    a)

    DMA

    b)

    Interrupt-driven I/O

    c)

    Program-controlled I/O

    d)

    Asynchronous I/O

    Ask AI

  5. Q1.5

    What does a branch prediction mechanism in a CPU help reduce?

    a)

    Data hazards

    b)

    Structural hazards

    c)

    Control hazards

    d)

    Clock cycle delays

    Ask AI

  6. Q1.6

    Which of the following is NOT a type of parallel processor architecture?

    a)

    SIMD

    b)

    MIMD

    c)

    SISO

    d)

    Multi-core

    Ask AI

  7. Q1.7

    Which cache replacement algorithm removes the least recently used block?

    a)

    FIFO

    b)

    LFU

    c)

    LRU

    d)

    Random Replacement

    Ask AI

  8. Q1.8

    Which technique is used to handle data hazards in pipelining?

    a)

    Increasing memory size

    b)

    Instruction scheduling

    c)

    Parallel processing

    d)

    Increasing clock speed

    Ask AI

  9. Q1.9

    Which addressing mode directly specifies the operand within the instruction?

    a)

    Direct Addressing

    b)

    Immediate Addressing

    c)

    Indirect Addressing

    d)

    Indexed Addressing

    Ask AI

  10. Q1.10

    A computer with 32 bit wide data bus uses $ 1K \times 8 $ static RAM memory chips. What is smallest memory that this computer have?

    a)

    32K

    b)

    8K

    c)

    16K

    d)

    24K

    Ask AI

Q.2 Solve both questions :

Ask AI

  1. Q2.1

    Describe the instruction execution cycle in a CPU. Explain some key features of the x86 architecture.

    Ask AI

  2. Q2.2

    Explain different addressing modes in a CPU with an examples.

    Ask AI

Q.3 Solve both questions :

Ask AI

  1. Q3.1

    Explain the Addition and Subtraction Algorithm with the help of flowchart.

    Ask AI

  2. Q3.2

    What is a Carry-look ahead fast adder? Draw the circuit of an 8-bit carry-look ahead adder using 4-bit carry look ahead adder.

    Ask AI

Q.4 Solve both questions :

Ask AI

  1. Q4.1

    Explain different cache replacement algorithms used in memory management.

    Ask AI

  2. Q4.2

    What are the different types of Registers? With the diagram show how the basic computer register connected to a common Bus.

    Ask AI

Q.5 Solve both questions :

Ask AI

  1. Q5.1

    Illustrate what are the challenges associated with concurrent access to memory in parallel processing?

    Ask AI

  2. Q5.2

    Describe different cache coherence protocols used in parallel processors.

    Ask AI

Q.6 Solve both questions :

Ask AI

  1. Q6.1

    A non-pipeline system takes 50ns to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of 10ns. Determine the speedup ratio of the pipeline for 100 task.

    Ask AI

  2. Q6.2

    What are pipeline hazards? Explain different types of hazards in pipelining.

    Ask AI

Q.7 Solve this question :

Ask AI

  1. Q7.1

    Explain Booth's algorithm for multiplication with the help of flowchart. Provide an example for its implementation.

    Ask AI

Q.8 Solve this question :

Ask AI

  1. Q8.1

    Describe different types of Input/Output transfers. Explain how data transfer take place through DMA.

    Ask AI

Q.9 Write short notes on any two of the following:-

Ask AI

  1. Q9.1

    a)

    RISC and CISC processor

    b)

    I/O device interfaces

    c)

    fixed and floating point representations

    d)

    Instruction Set Architecture

    Ask AI

2024V2105401

B.Tech 4th Semester Examination, 2024

03 Hours70 marks

Instructions

  • The marks are indicated in the right-hand margin.
  • There are NINE questions in this paper.
  • Attempt FIVE questions in all.
  • Question No. 1 is compulsory.

Q.1 Choose the correct answer of the following (any seven question only):

Ask AI

  1. Q1.1

    What is the first step in the instruction execution cycle?

    a)

    Decode

    b)

    Execute

    c)

    Fetch

    d)

    Store

    Ask AI

  2. Q1.2

    What is the advantage of carry look-ahead adders over ripple carry adders?

    a)

    Simplicity in design

    b)

    Increased latency

    c)

    Reduced power consumption

    d)

    Faster addition by reducing carry propagation delay

    Ask AI

  3. Q1.3

    Which type of control unit is faster but more difficult to modify?

    a)

    Hardwired Control Unit

    b)

    Microprogrammed Control Unit

    c)

    Cache Control Unit

    d)

    Memory Management Unit

    Ask AI

  4. Q1.4

    Which of the following I/O transfer methods involves the CPU polling the device until data is ready?

    a)

    DMA

    b)

    Interrupt-driven I/O

    c)

    Program-controlled I/O

    d)

    Asynchronous I/O

    Ask AI

  5. Q1.5

    What does a branch prediction mechanism in a CPU help reduce?

    a)

    Data hazards

    b)

    Structural hazards

    c)

    Control hazards

    d)

    Clock cycle delays

    Ask AI

  6. Q1.6

    Which of the following is NOT a type of parallel processor architecture?

    a)

    SIMD

    b)

    MIMD

    c)

    SISO

    d)

    Multi-core

    Ask AI

  7. Q1.7

    Which cache replacement algorithm removes the least recently used block?

    a)

    FIFO

    b)

    LFU

    c)

    LRU

    d)

    Random Replacement

    Ask AI

  8. Q1.8

    Which technique is used to handle data hazards in pipelining?

    a)

    Increasing memory size

    b)

    Instruction scheduling

    c)

    Parallel processing

    d)

    Increasing clock speed

    Ask AI

  9. Q1.9

    Which addressing mode directly specifies the operand within the instruction?

    a)

    Direct Addressing

    b)

    Immediate Addressing

    c)

    Indirect Addressing

    d)

    Indexed Addressing

    Ask AI

  10. Q1.10

    A computer with 32 bit wide data bus uses 1K×81K \times 8 static RAM memory chips. What is smallest memory that this computer have?

    a)

    32K

    b)

    8K

    c)

    16K

    d)

    24K

    Ask AI

Q.2 Solve both questions :

Ask AI

  1. Q2.1

    Describe the instruction execution cycle in a CPU. Explain some key features of the x86 architecture.

    Ask AI

  2. Q2.2

    Explain different addressing modes in a CPU with an examples.

    Ask AI

Q.3 Solve both questions :

Ask AI

  1. Q3.1

    Explain the Addition and Subtraction Algorithm with the help of flowchart.

    Ask AI

  2. Q3.2

    What is a Carry-look ahead fast adder? Draw the circuit of an 8-bit carry-look ahead adder using 4-bit carry look ahead adder.

    Ask AI

Q.4 Solve both questions :

Ask AI

  1. Q4.1

    Explain different cache replacement algorithms used in memory management.

    Ask AI

  2. Q4.2

    What are the different types of Registers? With the diagram show how the basic computer register connected to a common Bus.

    Ask AI

Q.5 Solve both questions :

Ask AI

  1. Q5.1

    Illustrate what are the challenges associated with concurrent access to memory in parallel processing?

    Ask AI

  2. Q5.2

    Describe different cache coherence protocols used in parallel processors.

    Ask AI

Q.6 Solve both questions :

Ask AI

  1. Q6.1

    A non-pipeline system takes 50ns to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of 10ns. Determine the speedup ratio of the pipeline for 100 task.

    Ask AI

  2. Q6.2

    What are pipeline hazards? Explain different types of hazards in pipelining.

    Ask AI

Q.7 Solve this question :

Ask AI

  1. Q7.1

    Explain Booth's algorithm for multiplication with the help of flowchart. Provide an example for its implementation.

    Ask AI

Q.8 Solve this question :

Ask AI

  1. Q8.1

    Describe different types of Input/Output transfers. Explain how data transfer take place through DMA.

    Ask AI

Q.9 Write short notes on any two of the following:-

Ask AI

  1. Q9.1

    • RISC and CISC processor
    • I/O device interfaces
    • fixed and floating point representations
    • Instruction Set Architecture
    a)

    RISC and CISC processor

    b)

    I/O device interfaces

    c)

    fixed and floating point representations

    d)

    Instruction Set Architecture

    Ask AI

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