A pipeline stage

A direct mapped cache memory with n blocks is nothing but which of the following set associative cache memory originations

The performance of a pipelined processor suffers if

A computer with cache access time of 100 ns, a main memory access time of 1000 ns, and a hit ratio of 0.9 produces an average access time of

Which of the following has no practical usage?

A micro programmed control unit

In memory- mapped I/O...

How many $ 128 \times 8 $ bit RAMs are required to design $ 32k \times 32 $ bit RAM?

The stalling of the processor due to the unavailability of the instruction is

The addressing mode, where you directly specify the operand value is called as

What are the hazards in pipeline architecture? Explain its types with suitable example.

What is addressing mode? Why do computers use addressing mode techniques? Explain two modes with example, which do not use address fields.

A 4-way set associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address space is 4GB. Find the number of bits for TAG, SET, and WORD fields in the address generated by CPU.

How is the virtual address mapped into physical address? What are the different methods of writing into cache?

What are the different types of instruction formats?

Discuss the different mapping techniques used in cache memories and their relative merits and demerits.

Design a 4-bit carry-look ahead adder and explain its operation with an example.

Consider a direct mapped cache with 8 cache blocks (numbered 0-7). If the memory block requests are in the following order 3, 5, 2, 8, 0, 63, 9, 16, 20, 17, 25, 18, 30, 24, 2, 63, 5, 82, 17, 24. What would be the status of cache blocks (block numbers residing in cache) at the end of the sequence.

What is DMA? Describe how DMA is used to transfer data from peripherals.

Differentiate between hardwired and micro programmed control unit. Explain each component of hardwired control unit organization.

What do you mean by asynchronous data transfer? Explain strobe control and hand shaking mechanism.

Show the systematic multiplication process of $ (20) \times (-19) $ using Booth's algorithm.

The stage delays in a four stages pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. What would be the throughput increases (in percentage) of the pipeline?

Explain IEEE standard for floating point representation with example.

A pipeline stage

A direct mapped cache memory with n blocks is nothing but which of the following set associative cache memory originations

The performance of a pipelined processor suffers if

A computer with cache access time of 100 ns, a main memory access time of 1000 ns, and a hit ratio of 0.9 produces an average access time of

Which of the following has no practical usage?

A micro programmed control unit

In memory- mapped I/O...

How many $128 \times 8$ bit RAMs are required to design $32k \times 32$ bit RAM?

The stalling of the processor due to the unavailability of the instruction is

The addressing mode, where you directly specify the operand value is called as

What are the hazards in pipeline architecture? Explain its types with suitable example.

What is addressing mode? Why do computers use addressing mode techniques? Explain two modes with example, which do not use address fields.

A 4-way set associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address space is 4GB. Find the number of bits for TAG, SET, and WORD fields in the address generated by CPU.

How is the virtual address mapped into physical address? What are the different methods of writing into cache?

What are the different types of instruction formats?

Discuss the different mapping techniques used in cache memories and their relative merits and demerits.

Design a 4-bit carry-look ahead adder and explain its operation with an example.

Consider a direct mapped cache with 8 cache blocks (numbered 0-7). If the memory block requests are in the following order 3, 5, 2, 8, 0, 63, 9, 16, 20, 17, 25, 18, 30, 24, 2, 63, 5, 82, 17, 24. What would be the status of cache blocks (block numbers residing in cache) at the end of the sequence.

What is DMA? Describe how DMA is used to transfer data from peripherals.

Differentiate between hardwired and micro programmed control unit. Explain each component of hardwired control unit organization.

What do you mean by asynchronous data transfer? Explain strobe control and hand shaking mechanism.

Show the systematic multiplication process of $(20) \times (-19)$ using Booth's algorithm.

The stage delays in a four stages pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. What would be the throughput increases (in percentage) of the pipeline?

Explain IEEE standard for floating point representation with example.

• Paging
• Memory interleaving
• Privileged and non-privileged instructions
• Locality of reference

The 8-bit encoding format used to store data in a computer is

The bus used to connect the monitor to the CPU is

The alternate way of writing the instruction, ADD #5, R1 is

The instruction fetch phase ends with

For converting a virtual address into the physical address, the programs are divided into

The transfer of large chunks of data with the involvement of the processor is done by

The computer architecture aimed at reducing the time of execution of instructions is

Which table handle stores the addresses of the interrupt handling sub-routines?

The situation wherein the data of operands are not available is called

The DMA controller has ___ registers.

List and briefly define the main structural components of a computer.

Discuss the design and logic of a microprogram sequence.

Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two fields the first contains the opcode and the remainder the immediate operand or an operand address.
What is the maximum directly addressable memory capacity (in bytes)?

Discuss the impact on the system speed if the microprocessor bus has (i) a 32-bit local address bus and a 16-bit local data bus, or (ii) a 16-bit local address bus and a 16-bit local data bus.

How many bits are needed for the program counter and the instruction register?

A set-associative cache has a block size of four 16-bit words and a set size of 2. The cache can accommodate a total of 4096 words. The main memory size that is cacheable is 64K 32 bits. Design the cache structure and show how the processor's addresses are interpreted.

Explain two techniques for enhancing the performance of computers with multiple execution pipelines.

Calculate (72530-13250) using ten's complement arithmetic. Assume rules similar to those for two's complement arithmetic.

List and briefly explain five important instruction set design issues.

The x86 architecture includes an instruction called decimal adjust after addition (DAA). DAA performs the following sequence of instructions :
if((AL AND OFH)>9) OR $ (AF=1) $ then $ AL \leftarrow AL+6 $; AF 1; else AF 0; endif;
if (AL> 9FH) OR $ (CF=1) $ then $ AL \leftarrow AL+60H $; CF-1; else CF 0; endif.
"H" indicates hexadecimal. AL is an 8-bit register that holds the result of addition of two unsigned 8-bit integers. AF is a flag set if there is a carry from bit 3 to bit 4 in the result of an addition. CF is a flag set if there is a carry from bit 7 to bit 8. Explain the function performed by the DAA instruction.

A non-pipelined processor has a clock rate of 2.5 GHz and an average CPI (cycles per instruction) of 4. An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays, such as latch delay, the clock rate of the new processor has to be reduced to 2 GHz.
1. What is the speedup achieved for a typical program?
2. What is the MIPS rate for each processor?

Briefly explain the two basic approaches used to minimize register-memory operations on RISC machines.

A computer has 16 registers, an ALU with 32 operations, and a shifter with 8 operations, all connected to a common bus system. (i) Formulate a control word for micro-operation. (ii) Show the bits of the control word that specify the micro-operation $ R4 \leftarrow R5+R6 $.

Let a be the percentage of a program code that can be executed simultaneously by n processors in a computer system. Assume that the remaining code must be executed sequentially by a single processor. Each processor has an execution rate of x MIPS.
Derive an expression for the effective MIPS rate when using the system for exclusive execution of this program, in terms of n, a and x.

If $ n=16 $ and $ x=4 $ MIPS, determine the value of that will yield a system performance of 40 MIPS.

The 8-bit encoding format used to store data in a computer is

The bus used to connect the monitor to the CPU is

The alternate way of writing the instruction, ADD #5, R1 is

The instruction fetch phase ends with

For converting a virtual address into the physical address, the programs are divided into

The transfer of large chunks of data with the involvement of the processor is done by

The computer architecture aimed at reducing the time of execution of instructions is

Which table handle stores the addresses of the interrupt handling sub-routines?

The situation wherein the data of operands are not available is called

The DMA controller has ___ registers.

List and briefly define the main structural components of a computer.

Discuss the design and logic of a microprogram sequence.

Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two fields the first contains the opcode and the remainder the immediate operand or an operand address.
What is the maximum directly addressable memory capacity (in bytes)?

Discuss the impact on the system speed if the microprocessor bus has (i) a 32-bit local address bus and a 16-bit local data bus, or (ii) a 16-bit local address bus and a 16-bit local data bus.

How many bits are needed for the program counter and the instruction register?

A set-associative cache has a block size of four 16-bit words and a set size of 2. The cache can accommodate a total of 4096 words. The main memory size that is cacheable is 64K 32 bits. Design the cache structure and show how the processor's addresses are interpreted.

Explain two techniques for enhancing the performance of computers with multiple execution pipelines.

Calculate (72530-13250) using ten's complement arithmetic. Assume rules similar to those for two's complement arithmetic.

List and briefly explain five important instruction set design issues.

The x86 architecture includes an instruction called decimal adjust after addition (DAA). DAA performs the following sequence of instructions :
if((AL AND OFH)>9) OR $ (AF=1) $ then $ AL \leftarrow AL+6 $; AF 1; else AF 0; endif;
if (AL> 9FH) OR $ (CF=1) $ then $ AL \leftarrow AL+60H $; CF-1; else CF 0; endif.
"H" indicates hexadecimal. AL is an 8-bit register that holds the result of addition of two unsigned 8-bit integers. AF is a flag set if there is a carry from bit 3 to bit 4 in the result of an addition. CF is a flag set if there is a carry from bit 7 to bit 8. Explain the function performed by the DAA instruction.

A non-pipelined processor has a clock rate of 2.5 GHz and an average CPI (cycles per instruction) of 4. An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays, such as latch delay, the clock rate of the new processor has to be reduced to 2 GHz.
1. What is the speedup achieved for a typical program?
2. What is the MIPS rate for each processor?

Briefly explain the two basic approaches used to minimize register-memory operations on RISC machines.

A computer has 16 registers, an ALU with 32 operations, and a shifter with 8 operations, all connected to a common bus system. (i) Formulate a control word for micro-operation. (ii) Show the bits of the control word that specify the micro-operation $ R4 \leftarrow R5+R6 $.

Let a be the percentage of a program code that can be executed simultaneously by n processors in a computer system. Assume that the remaining code must be executed sequentially by a single processor. Each processor has an execution rate of x MIPS.
Derive an expression for the effective MIPS rate when using the system for exclusive execution of this program, in terms of n, a and x.

If $ n=16 $ and $ x=4 $ MIPS, determine the value of that will yield a system performance of 40 MIPS.