Computer Architecture

How many $ 128 \times 8 $ bit RAMs are required to design $ 32k \times 32 $ bit RAM?

The sequence of events that happen during a typical fetch operation is

in case of pipelining processor, loop buffer is

The intradata transfer techniques are implemented using

The average memory access time for a machine with a cache hit rate of 90% where the cache access time is 10 ns and the memory access time is 100 ns is

The minimum time delay between the initiations of two independent memory operations is called

In case of vectored interrupt, interrupt vector means

A microprogrammed control unit

Relative addressing mode is used to write position independent code because

Which of the following holds data and processing instructions temporarily until the CPU needs it?

How do instruction set, compiler technology, CPU implementation and control, and cache and memory hierarchy affect the CPU performance? Justify the effects in terms of program length, clock rate and effective CPI.

How is virtual memory managed using paging and TLB? Explain with suitable example.

Explain register reference and memory reference instructions in detail with suitable examples.

Draw the block diagram of control unit of basic computer. Explain in detail with control timing diagrams.

Explain one, two and three-address instruction with suitable examples.

Give an integrated diagram, showing the TLB and cache operations for a logical/virtual address generated by a processor.

Explain the daisy chaining mechanism for bus arbitration. Analzye the three bus arbitration methods-daisy chaining, polling and independent requesting with respect to communication reliability in the even of hardware failures.

Give the block diagram of microprogram sequencer for a control memory and explain it properly.

What do you understand by hardwired control? Give various methods to design hardwired control unit. Describe any one with suitable example.

Describe autoincrement and autodecrement addressing modes with proper examples.

What is direct memory access? Explain. Give block diagram of circuitry required for direct memory access.

A digital computer has a common bus system of 16 registers of 32 bits each. The bus is constructed with multiplexers. (i) How many selection inputs are there in each multiplexer? (ii) What size of multiplexers is needed?

When do you say the floating point number is normalized? Explain how floating point representation of number is done. Represent the number (+46.25) as floating point binary number with 32 bits.

What are hazards in pipeline architecture? Explain its type with suitable example.

What is array processor? Explain SIMD array processor with suitable example.

A DMA controller transfers 16-bit words to memory using cycle stealing. The words are assembled from a device that transmits characters at the rate of 2400 characters per second. The CPU is fetching and executing instructions at an average rate of 1 million instructions per second. By how much will the CPU be slowed down because of DMA transfer?

How many $ 128 \times 8 $ bit RAMs are required to design $ 32k \times 32 $ bit RAM?

The sequence of events that happen during a typical fetch operation is

in case of pipelining processor, loop buffer is

The intradata transfer techniques are implemented using

The average memory access time for a machine with a cache hit rate of 90% where the cache access time is 10 ns and the memory access time is 100 ns is

The minimum time delay between the initiations of two independent memory operations is called

In case of vectored interrupt, interrupt vector means

A microprogrammed control unit

Relative addressing mode is used to write position independent code because

Which of the following holds data and processing instructions temporarily until the CPU needs it?

How do instruction set, compiler technology, CPU implementation and control, and cache and memory hierarchy affect the CPU performance? Justify the effects in terms of program length, clock rate and effective CPI.

How is virtual memory managed using paging and TLB? Explain with suitable example.

Explain register reference and memory reference instructions in detail with suitable examples.

Draw the block diagram of control unit of basic computer. Explain in detail with control timing diagrams.

Explain one, two and three-address instruction with suitable examples.

Give an integrated diagram, showing the TLB and cache operations for a logical/virtual address generated by a processor.

Explain the daisy chaining mechanism for bus arbitration. Analzye the three bus arbitration methods-daisy chaining, polling and independent requesting with respect to communication reliability in the even of hardware failures.

Give the block diagram of microprogram sequencer for a control memory and explain it properly.

What do you understand by hardwired control? Give various methods to design hardwired control unit. Describe any one with suitable example.

Describe autoincrement and autodecrement addressing modes with proper examples.

What is direct memory access? Explain. Give block diagram of circuitry required for direct memory access.

A digital computer has a common bus system of 16 registers of 32 bits each. The bus is constructed with multiplexers. (i) How many selection inputs are there in each multiplexer? (ii) What size of multiplexers is needed?

When do you say the floating point number is normalized? Explain how floating point representation of number is done. Represent the number (+46.25) as floating point binary number with 32 bits.

What are hazards in pipeline architecture? Explain its type with suitable example.

What is array processor? Explain SIMD array processor with suitable example.

A DMA controller transfers 16-bit words to memory using cycle stealing. The words are assembled from a device that transmits characters at the rate of 2400 characters per second. The CPU is fetching and executing instructions at an average rate of 1 million instructions per second. By how much will the CPU be slowed down because of DMA transfer?

Write the range of decimal integer can be represented by n-bit 2's complement representation.

Justify the statement "Stack computer consists of an operation code only with no address field".

What do you mean by Arithmetic shift left operation?

What do you mean by locality of reference?

What are the properties of an ideal instruction set computer.

Define the term hardware polling.

What do you mean by data hazards in pipelining?

Explain indirect address mode, and how the effective address in calculated in this case.

Explain the use of subroutine with the help of suitable example.

Why is read and write control lines in a DMA controller bidirectional? Under what condition and for what purpose are they used as inputs?

Explain the concept of virtual memory with the help of diagram. Explain how virtual address in mapped to actual physical address.

What is meant by Addressing Mode? Explain at least five different Addressing Modes with an example.

What are the different conflicts that will arise in pipeline (elaborate)? How do you remove the conflicts?

Explain Von Neumann Architecture. What are its drawbacks?

What is a page fault? What does a page fault signify? Explain the different page replacement algorithms which determine the page to be removed in case of full memory.

Why does I/O interrupt make more efficient use of the CPU? Explain the sequence of operations that take place in an interrupt driven I/O transfer.

How many ROM chips are required to produce a memory capacity of 4096 bytes? How many address lines are required to access the 4096 bytes? How many of these addresses will be common to all these chips?

Write the range of decimal integer can be represented by n-bit 2's complement representation.

Justify the statement "Stack computer consists of an operation code only with no address field".

What do you mean by Arithmetic shift left operation?

What do you mean by locality of reference?

What are the properties of an ideal instruction set computer.

Define the term hardware polling.

What do you mean by data hazards in pipelining?

Explain indirect address mode, and how the effective address in calculated in this case.

Explain the use of subroutine with the help of suitable example.

Why is read and write control lines in a DMA controller bidirectional? Under what condition and for what purpose are they used as inputs?

Explain the concept of virtual memory with the help of diagram. Explain how virtual address in mapped to actual physical address.

What is meant by Addressing Mode? Explain at least five different Addressing Modes with an example.

What are the different conflicts that will arise in pipeline (elaborate)? How do you remove the conflicts?

Explain Von Neumann Architecture. What are its drawbacks?

What is a page fault? What does a page fault signify? Explain the different page replacement algorithms which determine the page to be removed in case of full memory.

Why does I/O interrupt make more efficient use of the CPU? Explain the sequence of operations that take place in an interrupt driven I/O transfer.

How many ROM chips are required to produce a memory capacity of 4096 bytes? How many address lines are required to access the 4096 bytes? How many of these addresses will be common to all these chips?